Magnetoresistive Random Access Memory (MRAM), based on the integration of silicon CMOS with MTJ technology, is a major emerging technology that is highly competitive with existing semiconductor memories such as SRAM, DRAM, Flash, etc. An MRAM device is generally comprised of an array of parallel first conductive lines on a horizontal plane, an array of parallel second conductive lines on a second horizontal plane spaced above and formed in a direction perpendicular to the first conductive lines, and an MTJ element interposed between a first conductive line and a second conductive line at each crossover location. This so called “cross-point” MRAM structure is designed for high density but low speed. A first conductive line may be a digit line while a second conductive line is a bit line or vice versa. Alternatively, a first conductive line may be a bottom electrode that is a sectioned line while a second conductive line is a bit line (or digit line). Optionally, there is a high performance MRAM architecture that is based on a 1T1MTJ cell for high speed. There are typically other devices including transistors and diodes below the array of first conductive lines as well as peripheral circuits used to select certain MRAM cells within the MRAM array for read or write operations.
In FIG. 1, an MTJ element 6 is shown that is based on a tunneling magneto-resistance (TMR) effect wherein a stack of layers has a configuration in which two ferromagnetic layers are separated by a thin non-magnetic dielectric layer. In an MRAM device, the MTJ element is formed between a bottom electrode 5 such as a first conductive line and a top electrode 14 which is a second conductive line. The bottom electrode 5 also known as a bottom conductor typically has a seed layer/conductive layer/capping layer configuration and is used to connect the MTJ element 6 to the transistor (not shown). The bottom (seed) layer 7 in the MTJ element 6 is generally comprised of one or more seed layers that promote a smooth and dense crystal growth in overlying MTJ layers. Above the seed layer 7 is an antiferromagnetic (AFM) pinning layer 8 and a first ferromagnetic layer that is a “pinned” layer 9 on the AFM layer. The thin tunnel barrier layer 10 above the pinned layer 9 is generally comprised of a dielectric material such as AlOx that is formed by first depositing an Al layer and then performing an in-situ oxidation. The tunnel barrier layer 10 must be extremely uniform over the wafer since small AlOx thickness variations result in large variations in resistance. It follows that to achieve a uniform tunnel barrier, the bottom conductor 5 upon which the tunnel barrier layer 10 is formed must be very smooth and flat. A ferromagnetic “free” layer 11 is formed on the tunnel barrier layer 10 and is preferably less than 50 Angstroms thick to obtain low switching fields in the patterned bits. At the top of the MTJ stack is a capping layer 12.
The MTJ stack in FIG. 1 has a so-called bottom spin valve configuration. Alternatively, an MTJ stack may have a top spin valve configuration in which a free layer is formed on a seed layer followed by sequentially forming a tunnel barrier layer, a pinned layer, AFM layer, and a capping layer.
The pinned layer 9 has a magnetic moment that is fixed in the y direction by exchange coupling with the adjacent AFM layer 8 that is also magnetized in the y direction. The free layer 11 has a magnetic moment that is either parallel or anti-parallel to the magnetic moment in the pinned layer. The tunnel barrier layer 10 is so thin that a current through it can be established by quantum mechanical tunneling of conduction electrons. The magnetic moment of the free layer may switch in response to external magnetic fields and it is the relative orientation of the magnetic moments between the free and pinned layers that determines the tunneling current and therefore the resistance of the tunneling junction. When a sense current 15 is passed from the top electrode 14 to the bottom electrode 5 in a direction perpendicular to the MTJ layers, a lower resistance is detected when the magnetization directions of the free and pinned layers are in a parallel state (“1” memory state) and a higher resistance is noted when they are in an anti-parallel state or “0” memory state.
Referring to FIG. 2, the MTJ element 6 is shown interposed between the bottom conductor 5 and the top conductor 14 in an MRAM cell 20. The substrate 1 is comprised of a transistor (not shown) that is typically connected to the bottom conductor by a stud 4. A digit line 3 (word line in a 1T1MTJ) is formed below the MTJ element 6 and within a first insulation layer 2 that is usually a composite layer consisting of a stack of two or more dielectric layers on the substrate which are not shown in order to simplify the drawing. The MTJ element 6 contacts the top conductor 14 (bit line) through the capping layer 12 and is formed in a second insulation layer 13 that is disposed on the bottom conductor 5. From a top-down perspective (not shown), a plurality of MTJ elements is formed in an array between multiple rows of bottom conductors (word lines) and multiple columns of top conductors (bit lines). Each MRAM has its own bottom conductor line.
Switching of the free layer magnetization in the MTJ bit is accomplished by applying currents in orthogonal directions. For instance, the MTJ element may be elliptical in shape with a long axis running parallel to the underlying digit or word line 3. Currents i1 running transversely in the bit line 14 and bottom conductor 5 are orthogonal to the current i2 in the digit line (MTJ) or word line 3 (1T1MTJ). Thus, the current i1 provides the field parallel to the easy axis of the bit while the current i2 provides the perpendicular (hard axis) component of the field. The intersection of the conductive lines generates a peak field that is engineered to be just over the switching threshold of the MTJ.
In a read operation, the information stored in an MRAM cell is read by sensing the magnetic state (resistance level) of the MTJ element through a sense current flowing top to bottom through the cell in a current perpendicular to plane (CPP) configuration. During a write operation, information is written to the MRAM cell by changing the magnetic state in the free layer to an appropriate one by generating external magnetic fields as a result of applying bit line and word line currents in two crossing conductive lines, either above or below the MTJ element. In cross-point MRAM architecture, the top electrode or the bottom electrode participates in both read and write operations.
A high performance MTJ element is characterized by a high magnetoresistive (MR) ratio which is dR/R where R is the minimum resistance of the MTJ element and dR is the change in resistance observed by changing the magnetic state of the free layer. A higher dR/R improves the readout speed in an MRAM array. In order to achieve good tunnel barrier properties such as a specific junction resistance x area (RA) value and a high breakdown voltage (Vb), it is necessary to have a uniform tunnel barrier layer that is promoted by a smooth and flat bottom conductor. Present MRAM array technology is designed for a 0.3×0.6 micron MTJ bit size with an RA in the range of 3000 to 4000 ohm-μm2 and with a dR/R>35%.
Although a free layer made of a high spin polarization material such as NiFeCo, CoFe(25%), or CoFeB provides a high dR/R, the result is unfavorable magnetic properties such as high values for switching field (HC), HK, and magnetostriction (λS). On the other hand, moderate spin polarization materials such as NiFe(<20%) minimize λS and reduce HC and switching field distribution (σHC), but dR/R is normally below 30%. Therefore, for present generation devices (0.3×0.6 micron bits), an MTJ is needed wherein HC, HK, λS are acceptably low, dR/R is greater than 35%, and RA is in a desirable range of about 3000 to 4000 ohm-μm2. Moreover, for future generations (0.2×0.4 micron bits), an MTJ having RA<1000 ohm-μm2 and dR/R>40% is needed. To our knowledge, these objectives have not yet been reached.
In U.S. Pat. No. 6,703,654, a smooth bottom conductor comprised of a high melting point metal is formed on a NiCr seed layer to improve performance in an overlying MTJ film.
The performance of an MTJ element is enhanced according to U.S. Pat. No. 6,831,312 by incorporating an amorphous alloy such as CoFeB as the pinned layer and free layer in an MTJ stack. Boron is included in the alloy to control the recrystallization temperature and polarization of the resulting MTJ device.
In U.S. Pat. No. 6,743,641, surface planarity on a first conductor layer is improved prior to bit material deposition in an MRAM structure by depositing a second conductor layer comprised of Ta on the polished surface of the first conductor. The second conductor is lightly polished to remove a top portion thereof and thereby conformally cover rough portions of the first conductor.